With the continued increase in high-speed processing by various processing units, the need for higher-speed accessing of memory units located “off-chip” of such processing units has become increasingly critical. One example where such computer processing has become increasingly critical is in the field of telecommunications. Network elements are located across and within different networks in the telecommunications industry to process or switch all of the different packets that are received. In particular, a given network element includes a number of different ports to receive and transmit packets of data therefrom. Accordingly, upon receipt of a given packet of data on a port, a network element determines which port to transmit this packet out from. In a typical network element, there are a number of different line cards having a number of different ports that are each receiving and/or transmitting packets of data. These network elements must, therefore, be able to buffer and process or switch these packets at very high data rates.
Accordingly, certain network elements incorporate multiple processors and multiple memory units in order to process or switch all of these data packets being received. Different network elements incorporate different configurations for the incorporation of multiple processors and multiple memory units. In one such configuration, a network element establishes a one-to-one relationship between a given memory unit, such as a dynamic random access memory (DRAM), and a given processor such that temporary storage of data for this processor is provided by this particular memory unit. However, this one-to-one configuration between a processor and a memory unit may not allow for the optimal accessing of data from the memory units, as a given processor may only access one memory unit during operation.
In an alternative configuration, a network element allows for sharing of these multiple memory units by the multiple processors. Accordingly, one processor can access data from any of the multiple memory units. However, this configuration can also be problematic as bottlenecking may occur during the accessing of the different memory units when multiple processors may try to access data from the same memory unit at the same time.